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| White Electronic Designs WV3HG264M64EEU-D4 ADVANCED* 1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED FEATURES 200-pin, dual in-line memory module (SO-DIMM) Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 Utilizes 800*, 667*, 533 and 400 Mb/s DDR2 SDRAM components VCC = 1.8V 0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3, 4, 5 and 6 Adjustable data-output drive strength On-die termination (ODT) Posted CAS# latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM 64ms: 8,192 cycle refresh Gold edge contacts Dual Rank RoHS compliant JEDEC Package option * 200 Pin (SO-DIMM) * PCB - 30.00mm (1.181") TYP. DESCRIPTION The WV3HG264M64EEU is a 2x64Mx64 Double Data Rate DDR2 SDRAM high density SO-DIMM. This memory module consists of sixteen 64Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 200-pin SO-DIMM FR4 substrate. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option OPERATING FREQUENCIES PC2-3200 Clock Speed CL-tRCD-tRP * Consult factory for availability PC2-4200 266MHz 4-4-4 PC2-5300* 333MHz 5-5-5 PC2-6400* 400MHz 6-6-6 200MHz 3-3-3 February 2006 Rev. 2 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 51 DQS2 101 A1 151 DQ42 1 VREF 2 VSS 52 DM2 102 A0 152 DQ46 53 VSS 103 VCC 153 DQ43 3 VSS 4 DQ4 54 VSS 104 VCC 154 DQ47 5 DQ0 55 DQ18 105 A10/AP 155 VSS 6 DQ5 56 DQ22 106 BA1 156 VSS 7 DQ1 57 DQ19 107 BA0 157 DQ48 8 VSS 58 DQ23 108 RAS# 158 DQ52 9 VSS 59 VSS 109 WE# 159 DQ49 10 DM0 60 VSS 110 CS0# 160 DQ53 11 DQS0# 61 DQ24 111 VCC 161 VSS 12 VSS 62 DQ28 112 VCC 162 VSS 13 DQS0 63 DQ25 113 CAS# 163 NC 14 DQ6 64 DQ29 114 ODT0 164 CK1 65 VSS 115 CS1# 165 VSS 15 VSS 16 DQ7 66 VSS 116 A13 166 CK1# 17 DQ2 67 DM3 117 VCC 167 DQS6# 18 VSS 68 DQS3# 118 VCC 168 VSS 19 DQ3 69 NC 119 ODT1 169 DQS6 20 DQ12 70 DQS3 120 NC 170 DM6 21 VSS 71 VSS 121 VSS 171 VSS 22 DQ13 72 VSS 122 VSS 172 VSS 23 DQ8 73 DQ26 123 DQ32 173 DQ50 74 DQ30 124 DQ36 174 DQ54 24 VSS 25 DQ9 75 DQ27 125 DQ33 175 DQ51 26 DM1 76 DQ31 126 DQ37 176 DQ55 27 VSS 77 VSS 127 VSS 177 VSS 28 VSS 78 VSS 128 VSS 178 VSS 29 DQS1# 79 CKE0 129 DQS4# 179 DQ56 30 CK0 80 CKE1 130 DM4 180 DQ60 31 DQS1 81 VCC 131 DQS4 181 DQ57 32 CK0# 82 VCC 132 VSS 182 DQ61 83 NC 133 VSS 183 VSS 33 VSS 34 VSS 84 NC 134 DQ38 184 VSS 35 DQ10 85 NC 135 DQ34 185 DM7 36 DQ14 86 NC 136 DQ39 186 DQS7# 137 DQ35 187 VSS 37 DQ11 87 VCC 38 DQ15 88 VCC 138 VSS 188 DQS7 39 VSS 89 A12 139 VSS 189 DQ58 40 VSS 90 A11 140 DQ44 190 VSS 41 VSS 91 A9 141 DQ40 191 DQ59 42 VSS 92 A7 142 DQ45 192 DQ62 43 DQ16 93 A8 143 DQ41 193 VSS 44 DQ20 94 A6 144 VSS 194 DQ63 45 DQ17 95 VCC 145 VSS 195 SDA 46 DQ21 96 VCC 146 DQS5# 196 VSS 47 VSS 97 A5 147 DM5 197 SCL 48 VSS 98 A4 148 DQS5 198 SA0 49 DQS2# 99 A3 149 VSS 199 VCCSPD 50 NC 100 A2 150 VSS 200 SA1 WV3HG264M64EEU-D4 ADVANCED PIN NAMES Pin Name CK0,CK1 CK0#, CK1# CKE0, CKE1 RAS# CAS# WE# CS0#, CS1# A0-A9, A11-A13 A10/AP BA0,BA1 ODT0,ODT1 SCL SDA SA1,SA0 DQ0-DQ63 DM0-DM7 DQS0-DQS7 DQS0#-DQS7# VCC VSS VREF VCCSPD NC Function Clock Inputs, positive line Clock Inputs, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Auto precharge SDRAM Bank Address On-die termination control Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD address Data Input/Output Data Masks Data strobes Data strobes complement Core and I/O Power Ground Input/Output Reference SPD Power Spare pins, No connect February 2006 Rev. 2 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M64EEU-D4 ADVANCED FUNCTIONAL BLOCK DIAGRAM 3 ohm + 5% ? CKE1 ODT1 CS1# CKE0 ODT0 CS0# DQS0 DQS0# DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS CS0# O D DQS# T DM 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 C K E 0 DQS CS1# O D DQS# T DM 1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 C K E 1 DQS4 DQS4# DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS CS0# O D DQS# T DM 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 C K E 0 DQS CS1# O D DQS# T DM 1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 C K E 1 DQS1 DQS1# DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS CS0# O DQS# D DM T 0 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 0 DQS CS1# O DQS# D DM T 1 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 1 DQS5 DQS5# DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS CS0# O DQS# D DM T 0 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 0 DQS CS1# O DQS# D DM T 1 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 1 DQS2 DQS2# DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS CS0# O D DQS# T DM 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 C K E 0 DQS CS1# O D DQS# T DM 1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 C K E 1 DQS6 DQS6# DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS CS0# O D DQS# T DM 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 C K E 0 DQS CS1# O D DQS# T DM 1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 C K E 1 DQS3 DQS3# DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS CS0# O D DQS# T DM 0 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 0 DQS CS1# O D DQS# T DM 1 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 1 DQS7 DQS7# DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS CS0# O D DQS# T DM 0 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 0 DQS CS1# O D DQS# T DM 1 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 1 3 ohm BA0 - BA1 A0 - A13 RAS# CAS# WE# 5% DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs SCL SA0 SA1 SCL A0 SPD A1 A2 WP * Clock Wiring Clock Input SDA DDR2 SDRAMs 8 DDR2 SDRAMs 8 DDR2 SDRAMs *CK0/CK0# *CK1/CK1# * Wire per Clock Loading Table/Wiring Diagrams VCCSPD VREF VCC VSS Serial PD DDR2 SDRAMs DDR2 SDRAMs, VCC, VCCQ and VCCL DDR2 SDRAMs, SPD Notes : 1. All resistor values are 22 ohms 5% unless otherwise specified 2. BAx, Ax, RAS#, CAS#, WE# resistors : 3.0 Ohms 5%. February 2006 Rev. 2 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs DC OPERATING CONDITIONS All voltages referenced to VSS Rating Parameter Supply Voltage I/O Reference Voltage I/O Termination Voltage Symbol VCC VREF VTT Min. 1.7 0.49 x VCC VREF-0.04 Type 1.8 0.50 x VCC VREF WV3HG264M64EEU-D4 ADVANCED Max. 1.9 0.51 x VCC VREF+0.04 Units V V V Notes 1 2 Notes: 1. VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. ABSOLUTE MAXIMUM RATINGS Symbol VCC VIN, VOUT TSTG IL Parameter Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Input leakage current; Any input 0V TA = 25C, f = 100MHz Parameter Input Capacitance (A0~A13, BA0~BA1, RAS#, CAS#, WE#) Input Capacitance (CKE0, CKE1), (ODT0, ODT1) Input Capacitance (CS0#, CS1#) Input Capacitance (CK0, CK0#, CK1, CK1#) Input Capacitance (DM0 ~ DM7), (DQS0 ~ DQS7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 (667) CIN5 (534) Input Capacitance (DQ0 ~ DQ63) COUT1 (667) COUT1 (534) February 2006 Rev. 2 4 Min 20 12 12 12 9 9 9 9 Max 36 20 20 20 11 12 11 12 Units pF pF pF pF pF pF pF pF White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M64EEU-D4 ADVANCED OPERATING TEMPERATURE CONDITION Parameter Operating temperature Symbol TOPER Rating 0 to 85 Units C Notes 1, 2 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2 2. At 0C - 85C, operation temperature range, all DRAM specification will be supported. INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.300 Max VCC + 0.300 VREF - 0.125 Units V V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter Input High (Logic 1) Voltage DDR2-400 & DDR2-533 Input Low (Logic 1) Voltage DDR2-667 Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 Input Low (Logic 0) Voltage DDR2-667, DDR2-800 TBD Symbol VIH(DC) VIH(DC) VIL(DC) VIL(DC) Min VREF + 0.250 VREF + 0.200 Max VREF - 0.250 VREF - 0.200 Units V V V V February 2006 Rev. 2 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ICC SPECIFICATION Symbol ICC0* Proposed Conditions Operating one bank active-precharge; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING WV3HG264M64EEU-D4 ADVANCED 806 TBD 665 744 534 704 403 704 Units mA ICC1* Operating one bank active-read-precharge; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 TBD 864 824 824 mA ICC2P** TBD 128 128 128 mA ICC2Q** TBD 560 480 480 mA ICC2N** TBD 640 480 192 560 480 192 560 480 192 mA mA mA ICC3P** TBD TBD ICC3N** Active standby current; All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal TBD 880 800 800 mA ICC4W* TBD 1184 1024 944 mA ICC4R* TBD 1224 1064 944 mA ICC5** TBD 2400 2240 2240 mA ICC6** ICC7* TBD 128 128 128 mA Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING. TBD 1824 1824 1824 mA ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Note: * Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode. ** Value calculated reflects all module ranks in this operating condition. February 2006 Rev. 2 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs AC CHARACTERISTICS PARAMETER CL = 6 CL = 5 CL = 4 CL = 3 SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS tIPW tIS tIH tCCD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD WV3HG264M64EEU-D4 ADVANCED AC TIMING PARAMETERS & SPECIFICATIONS 806 MIN TBD TBD TBD TBD TBD TBD TBD 665 MAX TBD TBD TBD TBD TBD TBD TBD 534 MAX 8,000 8,000 8,000 0.55 0.55 MIN MAX MIN 403 MAX UNIT ps ps ps ps tCK tCK ps 125 +600 tAC MAX tAC MIN 150 275 0.35 400 450 tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2 300 350 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 350 475 2 MIN 3,000 3,750 5,000 0.45 0.45 MIN (tCH, tCL) -125 -450 Clock cycle time Clock 3,750 5,000 0.45 0.45 MIN (tCH, tCL) -125 -500 8,000 8,000 0.55 0.55 5,000 5,000 0.45 0.45 MIN (tCH, tCL) -125 -600 8,000 8,000 0.55 0.55 CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ...DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising ... setup time DQS falling edge from CK rising ... hold time DQS...DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input hold time TBD TBD TBD TBD TBD TBD 125 +450 tAC MAX 125 +500 tAC MAX ps ps ps ps ps ps tCK ps ps ns tCK tCK ps tCK tCK ps tCK tCK ps tCK tCK tCK tCK ps ps tCK TBD TBD tAC MIN 100 225 0.35 tAC MAX tAC MIN 100 225 0.35 tAC MAX tAC MAX TBD TBD Data TBD TBD TBD TBD TBD TBD TBD TBD 340 tHP - tQHS tQH - tDQSQ 0.35 0.35 -400 0.2 0.2 240 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 200 275 2 tHP - tQHS tQH - tDQSQ 0.35 0.35 -450 0.2 0.2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD +400 +450 +500 Data Strobe TBD TBD 1.1 0.6 0.6 WL + 0.25 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 250 375 2 1.1 0.6 1.1 0.6 0.6 WL + 0.25 0.6 WL + 0.25 TBD TBD TBD TBD TBD TBD TBD TBD AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page February 2006 Rev. 2 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs AC CHARACTERISTICS PARAMETER ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK,CK# uncertainty REFRESH to Active of Refresh to Refresh command internal WV3HG264M64EEU-D4 ADVANCED AC TIMING PARAMETERS (cont'd) 800 SYMBOL tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF TBD TBD TBD TBD TBD TBD 665 MAX TBD TBD TBD TBD TBD TBD TBD TBD 534 MAX MIN 60 7.5 15 37.5 45 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS + tCK + tIH 127.5 403 MAX MIN 65 7.5 15 37.5 45 7.5 15 tWR + tRP 10 15 tRP+tCK 2 tIS + tCK + tIH 127.5 MIN TBD TBD TBD TBD TBD TBD TBD TBD MIN 55 7.5 15 37.5 45 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS + tCK + tIH 127.5 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns tCK ns Command and Address 37.5 70,000 37.5 70,000 37.5 70,000 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 70,000 7.8 70,000 7.8 70,000 7.8 ns s ns tCK ps Self Refresh Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 7 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 tCK ps tCK ps ODT ODT turn-on (power-down mode) tAONPD TBD TBD ps ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any nonREAD command. CKE minimum high/low time tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE TBD TBD TBD TBD TBD TBD ps tCK tCK tCK tCK tCK tCK Power-Down TBD TBD TBD TBD TBD TBD AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. February 2006 Rev. 2 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M64EEU-D4 ADVANCED ORDERING INFORMATION FOR D4 Part Number WV3HG264M64EEU806D4xG* WV3HG264M64EEU665D4xG* WV3HG264M64EEU534D4xG WV3HG264M64EEU403D4xG Clock/Data Rate Speed 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3 tRCD 6 5 4 3 tRP 6 5 4 3 Height** 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP * Consult factory for availability NOTES: * RoHS product. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR D4 FRONT VIEW 67.75 (2.667) 67.45 (2.656) 3.80 (0.150) MAX 4.10(0.161) (2X) 3.90(0.154) 1.80 (0.071) (2X) 30.15 (1.187) 29.85 (1.175) 20.00 (0.787) TYP 6.00 (0.236) 2.55 (0.100) 1.10 (0.043) 0.90 (0.035) 1.00 (0.039) TYP 0.45 (0.018) TYP 63.60 (2.504) TYP 0.60 (0.024) TYP 2.15 (0.085) PIN 199 PIN 1 BACK VIEW PIN 200 47.40 (1.866) TYP 4.2 (0.165) TYP 11.40 (0.449) TYP PIN 2 ** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) February 2006 Rev. 2 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M64EEU-D4 ADVANCED PART NUMBERING GUIDE WV 3 H G 2 64M 64 E E U xxx D4 x G WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH x8 1.8V UNBUFFERED SPEED (Mb/s) PACKAGE 200 PIN COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = ROHS COMPLIANT February 2006 Rev. 2 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED WV3HG264M64EEU-D4 ADVANCED Revision History Rev # Rev 0 History Created Release Date February 2005 Status Advanced Rev 1 1.1 Updated AC specifications November 2005 Advanced Rev 2 2.1 Update Specifications * VCC * Maximum Rating Febraury 2006 Advanced February 2006 Rev. 2 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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